Last updated: 2025-06-20

17 Hardware Design And Verification jobs in Shanghai.

Hiring now: Serdespcie Ip Application Engineer Posts @ Synopsys, Spe Analog Eng @ Rambus, 高算力芯片端到端大模型Vla预研工程师 @ Boschgroup, Sr Asic Design Integration Engineer @ Tenafe, Sr Rd Engineer @ Ansys, Hw Engineer Technical Leader @ Cisco. Explore more at at jobswithgpt.com

🔥 Skills

ASIC (6) design (2) DDR5 (2) Verilog (2) Interface IP (2) Simulation (2) Verification (2) PCB design (2) semiconductor (2) signal integrity (2)

📍 Locations

Shanghai (13)

Synopsys

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choos…

Serdes/PCIe IP Application Engineer (post-sale)

Shanghai

  • Skills: Serdes, PCIe, ASIC, IP, design, integration, verification, low power design, silicon debug, customer interaction
  • Experience: Minimum 10 years of IP and/or ASIC Design/Verification/Applications experience is required
  • Type: Employee

Rambus

Rambus is a premier chip and silicon IP provider, known for its innovative memory interface chips and silicon IP that advance data center connectivity.

SPE Analog Engineering

Shanghai

  • Skills: analog design, mixed-signal circuit, high-performance, DDR5, DDR6, chip design, Verilog, Matlab, layout engineering, cross-functional teams
  • Experience: 10+ years of analog / mixed-signal circuit design experience
  • Type: Full-time

Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. We are powering the world’s most advanced technologies for chip design…

DDR/HBM controller IP Application Engineer

Shanghai

  • Skills: ASIC design, Interface IP, DDR, LPDDR, Integration guidance, Technical challenges, Simulation, Verification, RTL Synthesis, Silicon/System bring-up
  • Experience: 5 to 7 years of related design or customer experience
  • Type: Employee

Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck betwe…

SPE Signal Integrity

Shanghai

  • Skills: Signal Integrity, Power Integrity, DDR4, DDR5, simulation, EM theory, transmission line theory, package design, PCB design, high-speed memory
  • Experience: 10+ years of industry experience
  • Type: Full-time

Synopsys

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving…

ASIC Digital Design/Verification Engineer Architect

Shanghai

  • Skills: ASIC, digital verification, verification methodologies, Interface IP, problem-solving, team collaboration, project goals, advanced verification tools, communication skills, mentoring
  • Experience: Extensive experience in ASIC digital verification.
  • Type: Employee

BoschGroup

高算力芯片端到端大模型VLA预研工程师

Shanghai

  • Skills: 高算力芯片, 端到端, 大模型, VLA, 原型开发, 算法验证, 功能迭代, 感知, 导航, 训练模型

Tenafe

Tenafe is a newly established startup company which focus on leveraging revolutionary SSD Controller SOC development and related firmware/software systems solu…

Senior ASIC Design & Integration Engineer

Shanghai

  • Skills: ASIC, SOC, Design, Integration, Synthesis, Timing Closure, DFT, Coding, Verification, Simulation
  • Experience: 5+ years with a Bachelor's or 3+ years with a Master's
  • Type: Full-Time

Ansys

Senior R&D Engineer

Shanghai

  • Skills: software development, design, implementation, maintenance, testing, documentation, EDA, semiconductor, circuit analysis, programming
  • Experience: 5 years

BoschGroup

ASIC Layout Designer

Shanghai

  • Skills: ASIC, layout design, analog layout, IC integration, physical verification, MEMS sensor, tape-out, wafer foundry, digital layout, PDK

Cisco

Cisco designs and sells consumer electronics, networking, voice, and communications technology and services.

HW Engineer - Technical Leader

Shanghai

  • Skills: hardware systems, FPGA design, ASIC/System level, board bring up, high-end switch/router, power management, signal integrity, ethernet protocol, Python scripting, Verilog HDL
  • Type: full_time

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